The invention relates to the general field of integrated circuit manufacture with particular reference to trench filling by means of CMP.
From the outset, chemical etching has been used, in both liquid and gaseous environments, for the removal of material during the processing of semiconductor integrated circuits. Removal of material by mechanical means, namely polishing with a slurry of abrasive particles, was developed elsewhere, notably the optical industry, but found a place in the semiconductor industry in the early days for the polishing of silicon wafers. It was soon found, however, that semiconductor surfaces had to be free of mechanical damage, however slight, if they were to have satisfactory electrical properties.
To overcome the problems associated with purely mechanical polishing, the process called chemical mechanical polishing (CMP) was developed. As the name implies, surfaces subjected to CMP are exposed to both chemical and mechanical polishing simultaneously. What CMP achieved was the ability to remove material along an approximately planar etch front at reasonable rates without leaving behind a damaged surface. This made CMP highly attractive as a means for planarizing a surface and it has been used for this purpose by the semiconductor industry for some years.
The removal rate R of material from a surface undergoing CMP can be represented by equation 1 as follows:
R=k1PV+k2V+k3xe2x80x83xe2x80x83(1)
where
P is the pressure between the slurry-bearing platten and the wafer,
V is the relative velocity between the surface and the platten,
k1 is a constant whose value depends on the various parameters associated with the mechanical component (slurry particle size, density, hardness, etc.),
k2 is a constant associated with hydrodynamic aspects of the system such as viscosity, surface tension, etc., and
k3 is a constant whose value depends on the various parameters associated with the chemical component (etchant concentration, temperature, refresh rate, etc.). Included in k3 would be the effects of any inhibitor that has been added to the etchant. Inhibitors form a self-limiting layer of etch-resistant material on the surface that is being etched, thereby halting the chemical attack until this limiting layer has been removed through mechanical means.
Although, as already implied, CMP has enjoyed great success as a planarization technique, it is not without its problems. A particular example of this is when a surface comprising a mix of hard and soft materials needs to be planarized. This situation arises during the formation of damascene wiring where lines are buried within a dielectric surface rather than lying on top of it.
Referring now to FIG. 1, we show a schematic cross-section of a dielectric layer 11 (comprising the top-most layer of an integrated circuit wafer) in whose upper surface several trenches, such as 13 and 14, have previously been formed. Copper layer 12 has been deposited over 11 in a sufficient quantity to ensure that all the trenches have been over-filled with the copper. CMP is now to be used to remove all copper that is not in the trenches, i.e. leaving the trenches just-filled while at the same time removing all traces of copper from everywhere else on layer 11""s upper surface.
A typical result obtained using CMP technology of the prior art is illustrated in FIG. 2. At the process point where the surface of 11 appears to be free of copper, it is found that considerable dishing of the trenches has occurred at 23 and 24 so that, instead of being just-filled, the trenches are under-filled. This is a consequence of the fact that, as the surface of 11 was being approached, the polish rate above the hard dielectric became significantly slower relative to the polish rates over areas where copper extended for a significant depth.
In practice it is often necessary to continue CMP beyond the stage illustrated in FIG. 2 because of residual copper traces still present on surfaces removed from the trenches. The result is that dishing becomes even more pronounced, as illustrated in FIG. 3, where trenches 33 and 34 are seen to be under-filled to the point of having almost no copper in them.
The present invention teaches how damascene wiring may be formed in which the trenches are just-filled with copper while at the same time removing all traces of copper everywhere else. A routine search of the prior art was performed but no references that teach the solution provided by the present invention were found. Several references of interest were, however, encountered. For example, Krishnan et al. (U.S. Pat. No. 5,380,546) allow dishing to occur but then they deposit a second metal layer which, in addition to being a barrier material, has polishing properties similar to the surrounding silicon oxide, so proper planarization is now possiblexe2x80x94i.e. the locations where dishing had occurred become backfilled with a barrier layer material.
Sasaki et al. (U.S. Pat. No. 5,770,095) describe a two-step etching process:
(a) purely mechanical, which is fast and planar but which causes gross surface damage, followed by
(b) conventional CMP, which is slower but which removes surface damage.
They also do CMP with, and without, an inhibitor, and CMP at room temperature followed by CMP at low temperature.
Sandhu et al. (U.S. Pat. No. 5,300,155) adjust the chemical contribution to the total CMP process by varying the temperature, first at room temperature and then at a lower temperature.
Walsh (U.S. Pat. No. 4,450,652) controls the temperature of a conventional (not CMP) system by varying the pressure on the wafers. This causes the temperature to change, thus allowing a closed loop to be used to keep the temperature constant through adjustment of the pressure.
Shamouillan et al. (U.S. Pat. No. 5,584,146) improve polishing uniformity by including conduits in the polishing pad for more efficient removal of the slurry.
Morimoto et al. (U.S. Pat. No. 5,104,828) find that uniformity during conventional polishing (not CMP) is improved by polishing at temperatures that are substantially below room temperature.
It has been an object of the present invention to provide a process for performing chemical mechanical polishing without the introduction of dishing.
Another object of the invention has been that said process be suitable for just-filling, with copper, trenches etched in the surface of a silicon wafer.
A further object of the invention has been that said process be fully compatible with existing integrated circuit manufacturing techniques.
These objects have been achieved by performing CMP as a two-step process. After trenches have been formed over-filled with copper, in a first embodiment of the invention a pad having high compressibility is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A pad having low compressibility is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.